The present invention relates to semiconductor devices and fabrication methods of the same, and more particularly, to a semiconductor device incorporated with electronic components such as passive components, and a method for fabricating the semiconductor device.
Generally, in order to desirably improve performances and functionality, semiconductor devices are often made in association with electronic components such as passive components. For example, U.S. Pat. Nos. 5,264,730, 5,311,405, 5,811,880, 5,825,628 and 6,316,828 disclose the incorporation of passive components on substrates for use in BGA (ball grid array) semiconductor packages, which passive components are purposed in enhancing overall electrical functions of the semiconductor packages.
Such a substrate with passive components being mounted thereon for use in a semiconductor device is illustrated in FIG. 9, wherein the passive components 40 such as resistors or capacitors are preferably disposed on a ground ring 13 and a power ring 12 of the substrate 10 at positions close to a chip 20 that is accommodated on the substrate 10. In particular, the passive components 40 are most preferably positioned at four corners in proximity to the chip 20, respectively.
However, as the passive components 40 occupied certain layout area on the substrate 10, pitches P between adjacent bond fingers 11 that are located between two passive components 40, are necessarily reduced from conventional dimensions of 0.150 mm to fine pitches such as 0.125 mm. This thereby significantly increases the fabrication costs.
Besides, the passive components 40 also adversely affect trace routability on the substrate 10; routing area and space for conductive traces (not shown) formed on the substrate 10 are both restricted by the arrangement of the passive components 40. On the contrary, in concern of complying with trace routability of the substrate 10, the passive components 40 must be arranged in a manner as not to interfere with the conductive traces formed on the substrate 10; this limits the number and positioning of the passive components 40 to be adopted in semiconductor devices.
Moreover, in case of the passive components 40 being disposed at peripheral positions instead of the corners nearby the chip 20 according to practical requirements, bonding wires 30 are formed to extend from the chip 20 and across the passive components 40, for electrically connecting bond pads 21 of the chip 20 to the corresponding bond fingers 11 on the substrate 10. However, as shown in FIG. 10, short circuit may easily occur as the bonding wires 30 come into contact with edges of the passive components 40, which thereby degrades the wire bonding quality and product reliability. Although this short-circuiting problem can be solved by pre-encapsulating the passive components 40 with an insulating material before forming the bonding wires 30, this pre-encapsulation process would undesirably increase complexity and costs in fabrication.
In response to the above-mentioned drawbacks, U.S. Pat. No. 5,670,824 discloses a type of substrate integrally formed with passive components, which substrate can be disposed underneath a chip for carrying the chip thereon. However, since conventional passive components such as resistors or capacitors are not suitably applied to this integration type of substrate, forming the integration substrate requires particularly designed passive components, and significantly raises the fabrication costs. Such an expensive substrate is hard to be commercialized and widely used in semiconductor industry.
Furthermore, Taiwan Patent Application No. 89121891 discloses a semiconductor structure illustrated in FIG. 11, in which a passive component 40 is directly mounted on and electrically connected to a chip 20 that is accommodated on a substrate 10. However, this semiconductor structure is rather complexly made, which needs to pre-form a plurality of connection pads 22 on the chip 20 for subsequently attaching the passive component 40 thereto. These connection pads 22 are then subjected to under bumping metalization, so as to electrically connect the connection pads 22 to solder paste that is applied for adhering the passive component 40 onto the connection pads 22. As a result, fabrication of this semiconductor structure is considerably complicated and cost-ineffective to implement.
Another embodiment of the semiconductor structure disclosed by the foregoing Taiwan patent, as shown in FIG. 12, involves the forming of conductive wires 42, 43 for electrically connecting the passive component 40 that is directly mounted on the chip 20 to a power ring 12 and a ground ring 13 on the substrate 10. However, contact terminals (not shown) formed on the passive component 40 for wire bonding use are not satisfactorily surface-flat, making a conventional wire bonding machine not able to, operate at the contact terminals for forming the conductive wires 42, 43. Moreover, if the contact terminals of the passive component 40 are not plated with gold, the wire bonding process cannot be implemented either. Therefore, since this semiconductor structure is hardly fabricated in large scale by using currently available equipment and processes, it is potentially low in demand in the market.
In accordance with the foregoing described, the present invention provides a novel, advanced and practical semiconductor device and a fabrication method thereof, so as to overcome the multiple drawbacks recited above in the prior arts.
A primary objective of the present invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, in which fine-pitch arrangement of bond fingers on a substrate needs not to be adopted.
Another objective of the invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, in which trace routability of a substrate, and number and positioning of the electronic components are not particularly limited for use in the semiconductor device.
Still another objective of the invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, which can prevent the occurrence of short circuit caused by bonding wires coming into contact with the electronic components.
A further objective of the invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, in which an expensive substrate integrated with electronic components needs not to be used, thereby making fabrication costs significantly reduced.
A further objective of the invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, in which no connection pads for mounting the electronic components thereon need to be formed on a chip, and thus no under bumping metalization for the connection pads is necessarily performed, so that fabrication processes and costs can be simplified and reduced, respectively.
A further objective of the invention is to provide a semiconductor device incorporated with electronic components such as passive components and a fabrication method of the semiconductor device, in which a conventional wire bonding machine is suitably applied for forming bonding wires, and the semiconductor device can be fabricated in a batch manner by using currently available processes and equipment.
In accordance with the above and other objectives, the present invention proposes a semiconductor device and a fabrication method of the same.
The semiconductor device of the invention comprises:
at least one electronic component having a first surface and a second surface;
a first substrate having a first surface and a second surface, wherein the second surface of the electronic component is electrically connected to the first surface of the first substrate;
a semiconductor chip having a first surface and a second surface;
a second substrate having a first surface and a second surface, wherein the second surface of the semiconductor chip is attached to the first surface of the second substrate, which combined structure of the semiconductor chip and the second substrate accommodates the first substrate that is mounted with the electronic component thereon in a manner that, for example, the second surface of the first substrate is attached to the first surface of the semiconductor chip or to the first surface of the second substrate, or to other suitable positions;
a plurality of bonding wires for establishing electrical connection among the first surface of the semiconductor chip, the first surface of the first substrate and the first surface of the second substrate;
an encapsulant formed on the first surface of the second substrate, for encapsulating the electronic component, the first substrate, the semiconductor chip and the bonding wires; and
a plurality of solder balls implanted on the second surface of the second substrate.
The fabrication method of the foregoing semiconductor device of the invention comprises the steps of:
preparing a first substrate, at least one electronic component, a semiconductor chip and a second substrate, each of which has a first surface and a second surface;
electrically connecting the second surface of the electronic component to the first surface of the first substrate;
attaching the second surface of the semiconductor chip to the first surface of the second substrate;
disposing the first substrate mounted with the electronic component on combined structure of the semiconductor chip and the second substrate in a manner that, for example, the second surface of the first substrate is attached to the first surface of the semiconductor chip or to the first surface of the second substrate, or to other suitable positions;
forming a plurality of bonding wires for establishing electrical connection among the first surface of the semiconductor chip, the first surface of the first substrate and the first surface of the second substrate;
forming an encapsulant on the first surface of the second substrate, for encapsulating the electronic component, the first substrate, the semiconductor chip and the bonding wires; and
implanting a plurality of solder balls on the second surface of the second substrate.
The foregoing semiconductor device and its fabrication method of the invention can also be suitably applied to a leadframe-based semiconductor device, wherein the second surface of the first substrate mounted with the electronic component thereon is attached to the first surface of the semiconductor chip.